Digital clock

Results: 222



#Item
41Sampling clock 28.8MHz ADC  IF to Baseband

Sampling clock 28.8MHz ADC IF to Baseband

Add to Reading List

Source URL: superkuh.com

Language: English - Date: 2013-02-20 15:35:51
42

PDF Document

Add to Reading List

Source URL: www.pcisig.com

Language: English
4313  Combination Locks This circuit uses 4013 D-type bistable flip-flops (D stands for data). Each flipflop has a data input and a clock input. The voltage applied to the input is transferred to the Q output at the instan

13 Combination Locks This circuit uses 4013 D-type bistable flip-flops (D stands for data). Each flipflop has a data input and a clock input. The voltage applied to the input is transferred to the Q output at the instan

Add to Reading List

Source URL: www.saburchill.com

Language: English - Date: 2006-01-01 10:01:19
44Electronic circuits / Electromagnetism / Audio engineering / Digital audio / Field-programmable gate array / Analog-to-digital converter / Word clock / Sampling rate / Sample and hold / Digital signal processing / Electronic engineering / Electronics

 Danville Signal dspstak™ a9238 • Dual 50 Ohm Inputs (SMA Connectors) • Up to 25M/s Sample Rate in Two Channel Mode

Add to Reading List

Source URL: www.danvillesignal.com

Language: English - Date: 2012-10-12 11:20:56
45 | www.iCoolSport.com International +Australia +iCool Touch Screen Memory Battery Replacement AND RE-SETTING SYSTEM CLOCK RESET

| www.iCoolSport.com International +Australia +iCool Touch Screen Memory Battery Replacement AND RE-SETTING SYSTEM CLOCK RESET

Add to Reading List

Source URL: www.icoolsport.com

Language: English - Date: 2013-06-17 22:54:08
46DVB Master™ III Tx Enhanced DVB-ASI PCI Transmit Interface Card with Fine Tuning, Auto Null Packet Insertion, Accurate Clock (25 ppm), and Jitter Management in Firmware

DVB Master™ III Tx Enhanced DVB-ASI PCI Transmit Interface Card with Fine Tuning, Auto Null Packet Insertion, Accurate Clock (25 ppm), and Jitter Management in Firmware

Add to Reading List

Source URL: www.dveo.com

Language: English - Date: 2013-11-04 15:59:13
47DVB Master™ FD PCIe LP Advanced Full Duplex DVB-ASI PCIe Send and Receive Low Profile Interface Card with Black Burst Sync Input in a Low Profile Card with Accurate Clock, Jitter Management,

DVB Master™ FD PCIe LP Advanced Full Duplex DVB-ASI PCIe Send and Receive Low Profile Interface Card with Black Burst Sync Input in a Low Profile Card with Accurate Clock, Jitter Management,

Add to Reading List

Source URL: www.dveo.com

Language: English - Date: 2014-05-13 14:28:04
48Datasheet  Power Compiler Power Optimization in Design Compiler  Overview

Datasheet Power Compiler Power Optimization in Design Compiler Overview

Add to Reading List

Source URL: www.synopsys.com

Language: English - Date: 2015-02-18 14:15:51
49Prix Ars Electronica 09 The 2009 Prix Ars Electronica received 3,017 entries from 68 countries. The jury of top international experts convened for three days (April 17-19)—deliberating practically ‘round-the-clock—

Prix Ars Electronica 09 The 2009 Prix Ars Electronica received 3,017 entries from 68 countries. The jury of top international experts convened for three days (April 17-19)—deliberating practically ‘round-the-clock—

Add to Reading List

Source URL: www.aec.at

Language: English - Date: 2011-08-25 06:17:48
50STARS: A System for Tuning and Actively Reconfiguring SoC Links Gregory Diamos and Sudhakar Yalamanchili School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA, USA Email: { gtg250v@mail

STARS: A System for Tuning and Actively Reconfiguring SoC Links Gregory Diamos and Sudhakar Yalamanchili School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA, USA Email: { gtg250v@mail

Add to Reading List

Source URL: www.gdiamos.net

Language: English - Date: 2011-06-30 03:27:08